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ST72321 数据表(PDF) 15 Page - STMicroelectronics |
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ST72321 数据表(HTML) 15 Page - STMicroelectronics |
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15 / 189 page  ST72321 15/189 002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W 002Bh SICSR System Integrity Control/Status Register 000x 000x b R/W 002Ch 002Dh MCC MCCSR MCCBCR Main Clock Control / Status Register Main Clock Controller: Beep Control Register 00h 00h R/W R/W 002Eh to 0030h Reserved Area (3 Bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh TIMER A TACR2 TACR1 TACSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register3 Timer A Input Capture 2 Low Register3 Timer A Output Compare 2 High Register3 Timer A Output Compare 2 Low Register3 00h 00h xxxx x0xx b xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0040h Reserved Area (1 Byte) 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh TIMER B TBCR2 TBCR1 TBCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register 00h 00h xxxx x0xx b xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h SCI SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register C0h xxh 00h x000 0000b 00h 00h --- 00h Read Only R/W R/W R/W R/W R/W R/W Address Block Register Label Register Name Reset Status Remarks |
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