ST72321 datasheet(165/189 Pages) STMICROELECTRONICS

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ST72321

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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)

12.11.2 I

2C - Inter IC Control Interface

Subject to general operating conditions for VDD,

fCPU, and TA unless otherwise specified.

Refer to I/O port characteristics for more details on

the input/output alternate function characteristics

(SDAI and SCLI). The ST7 I2C interface meets the

requirements of the Standard I2C communication

protocol described in the following table.

Figure 95. Typical Application with I

2C Bus and Timing Diagram 4)

Notes:

1. Data based on standard I2C protocol requirement, not tested in production.

2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL.

3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of

SCL signal.

4. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

5. At 4MHz fCPU, max.I

2C speed (400kHz) is not achievable. In this case, max. I2C speed will be approximately 260KHz.

Symbol

Parameter

Standard mode I2C

Fast mode I2C5)

Unit

Min 1)

Max 1)

Min 1)

Max 1)

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

0 3)

0 2)

900 3)

tr(SDA)

tr(SCL)

SDA and SCL rise time

1000

20+0.1Cb

300

tf(SDA)

tf(SCL)

SDA and SCL fall time

300

20+0.1Cb

300

th(STA)

START condition hold time

4.0

0.6

µs

tsu(STA)

Repeated START condition setup time

4.7

0.6

tsu(STO)

STOP condition setup time

4.0

0.6

µs

tw(STO:STA) STOP to START condition time (bus free)

4.7

1.3

µs

Capacitive load for each bus line

400

REPEATED START

START

STOP

START

tf(SDA)

tr(SDA)

tsu(SDA)

th(SDA)

tf(SCK)

tr(SCK)

tw(SCKL)

tw(SCKH)

th(STA)

tsu(STO)

tsu(STA)

tw(STO:STA)

SDA

SCK

4.7k

Ω

SDAI

ST72XXX

SCLI

VDD

100

Ω

100

Ω

VDD

4.7k

Ω

I2CBUS

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