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03C8T6 数据表(PDF) 29 Page - STMicroelectronics |
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03C8T6 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 67 page  STM32F103xx Electrical characteristics 29/67 5.3.5 Supply current characteristics The current consumption is measured as described in Figure 10: Current consumption measurement scheme. Maximum current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except if it is explicitly mentioned ● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 7. Table 11. Maximum current consumption in Run and Sleep modes(1) Symbol Parameter Conditions FHCLK Typ(2) Max(3) Unit TA = 85 °C TA= 105 °C IDD Supply current in Run mode External clock with PLL, code running from Flash, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK 72 MHz 36 TBD TBD mA 48 MHz 30 TBD TBD 36 MHz 22 TBD TBD 24 MHz 21 TBD TBD External clock, PLL stopped, code running from Flash, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK 8 MHz 10 TBD TBD External clock with PLL, code running from RAM, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK 72 MHz 32 45 47 48 MHz 22 31 33 36 MHz 13 18 20 24 MHz 11 15 17 External clock, PLL stopped, code running from RAM, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK 8 MHz 4.5 TBD TBD Supply current in Sleep mode External clock with PLL, code running from RAM or Flash, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK 72 MHz 22 35 37 mA 48 MHz 14 23 25 36 MHz 13 22 24 24 MHz 10 17 19 External clock, PLL stopped, code running from RAM or Flash, all peripherals enabled (see RCC register description): fPCLK1= fHCLK/2, fPCLK2 = fHCLK 8 MHz 3.5 TBD TBD 1. TBD stands for to be determined. 2. Typical values are measured at TA = 25 °C, and VDD = 3.3 V 3. Data based on characterization results, tested in production at VDmax, fHCLK max. TAmax, and code executed from RAM. |
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