AD8311

Rev. A | Page 12 of 24

The intercept need not correspond to a physically realizable

part of the signal range for the log amp. Thus, the specified

intercept is −58.9 dBm at 0.1 GHz, whereas the smallest input

for accurate measurement (a +1 dB error) at this frequency is

higher, about −44.5 dBm. At 2.5 GHz, the +1 dB error point

shifts to −47.7 dBm. This positioning of the intercept is

deliberate and ensures that the VSET voltage is within the

capabilities of certain digital-to-analog converters (DACs),

whose outputs cannot swing below 200 mV. Figure 26 shows the

100 MHz response of the AD8311; the vertical axis represents

not the output (at the VAPC pin) but the value required at the

power control pin (VSET) to null the control loop. This is

explained in the Controller-Mode Log Amps section.

1.5

0

100

μV

–67dBm

1V (RMS)

13dBm (RE 50

Ω)

VIN, PIN

1mV

–47dBm

10mV

–27dBm

100mV

–7dBm

1.0

0.5

SLOPE = 23.8mV/dB

1.211V @ –8dBm

IDEAL

448mV @ –40dBm

ACTUAL

–58.9dBm

Figure 26. Basic Calibration of the AD8311 at 0.1 GHz

CONTROLLER-MODE LOG AMPS

The AD8311 combines the two key functions required for the

measurement and control of the power level over a moderately

wide dynamic range. First, it provides the amplification needed

to respond to small signals in a chain of four amplifier/limiter

cells (see Figure 25), each having a small signal gain of 10 dB

and a bandwidth of approximately 3.5 GHz. At the output of

each of these amplifier stages is a full-wave rectifier, essentially a

square law detector cell that converts the RF signal voltages to a

fluctuating current having an average value that increases with

signal level. A further passive detector stage is added before the

first stage. These five detectors are separated by 10 dB, spanning

some 50 dB of dynamic range. Their outputs are each in the

form of a differential current, making summation a simple

matter. It is readily shown that the summed output can closely

approximate a logarithmic function. The log conformance

error, which is the overall accuracy at the extremes of this total

range viewed as the deviation from an ideal logarithmic

response, can be judged by reference to Figure 6, which shows

that errors across the central 40 dB are moderate.

In a device intended for measurement applications, this current

would then be converted to an equivalent voltage, to provide the

log(VIN) function shown in Equation 1. However, the design of

the AD8311 differs from standard practice in that its output

needs to be a low noise control voltage for an RF power

amplifier, not a direct measure of the input level. Further, it is

highly desirable that this voltage be proportional to the time-

integral of the error between the actual input VIN and a dc

voltage VSET (applied to Pin 3, VSET). VSET defines the setpoint,

a target value for the power level typically generated by a DAC.

This is achieved by converting the difference between the sum

of the detector outputs (still in current form) and an internally

generated current proportional to VSET to a single-sided

current-mode signal. This, in turn, is converted to a voltage (at

Pin 4, FLTR, the low-pass filter capacitor node) to provide a

close approximation to an exact integration of the error

between the power present in the termination at the input of the

AD8311 and the setpoint voltage. Finally, the voltage developed

across the ground-referenced filter capacitor CFLT is buffered by

a special low noise amplifier of low voltage gain (×1.35) and

presented at Pin 2 (VAPC) for use as the control voltage for the

RF power amplifier. This buffer can provide rail-to-rail swings

and can drive a substantial load current, including large

capacitors. Note that the RF power amplifier is assumed to have

a positive slope with RF power increasing monotonically with

an increasing APC control voltage.

CONTROL LOOP DYNAMICS

In order to understand how the AD8311 behaves in a complete

control loop, an expression for the current in the integration

capacitor as a function of the input PIN and the setpoint voltage

VSET must be developed. Refer to Figure 27.

RF PA

DIRECTIONAL

COUPLER

POUT

PCW

RF DRIVE:

UP TO

2.5GHz

SETPOINT

INTERFACE

LOGARITHMIC

RF DETECTION

SUBSYSTEM

3

6

VSET

RFIN

4

CFLT

FLTR

2

VAPC

ISET = VSET/RSET

IDET

IERR

IDET = ISLP PIN + IINT

VSET

VIN

1.35

Figure 27. Behavioral Model of the AD8311