AD8311 datasheet(15/24 Pages) AD

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AD8311

Rev. A | Page 15 of 24

TRANSIENT RESPONSE

The time domain response of power amplifier control loops,

using any kind of controller, is only partially determined by the

choice of filter. In the case of the AD8311, the filter has a true

integrator form 1/sT as shown in Equation 7, with a time

constant given by Equation 8. The large signal step response is

also strongly dependent on the form of the gain-control law.

Nevertheless, some simple rules can be applied. When the filter

capacitor CFLT is very large it dominates the time domain

response, but the incremental bandwidth of this loop still varies

as VAPC traverses the nonlinear gain-control function of the PA.

This bandwidth is highest at the point where the slope of the

tangent drawn on the PA power-control curve is greatest—that

is, for power outputs near the center of the PA’s range—and is

much reduced at both the minimum and the maximum power

levels, where the slope of the gain control curve is lowest due to

its S-shaped form.

Using smaller values of CFLT, the loop bandwidth generally

increases in inverse proportion to its value. Eventually, however,

a secondary effect appears due to the inherent phase lag in the

power amplifier’s control path, some of which can be due to

parasitic or deliberately added capacitance at the VAPC pin. This

results in the characteristic poles in the ac loop equation moving

off the real axis and thus becoming complex (and somewhat

resonant). This is a classic aspect of control loop design. The

lowest permissible value of CFLT needs to be determined

experimentally for a particular amplifier. For GSM and DCS

power amplifiers, CFLT typically ranges from 150 pF to 300 pF.

In many cases, some improvement in the worst-case response

time can be achieved by including a small resistor in series with

CFLT; this generates an additional zero in the closed-loop

transfer function, which serves to cancel a higher order pole in

the overall loop. A more complex filter network can be used to

minimize the settling time of the loop—for example, a

combination of the main capacitor, CFLT, shunted by a second

capacitor and resistor series.

MOBILE HANDSET POWER CONTROL EXAMPLE

Figure 31 shows a complete power amplifier control circuit for a

dual mode handset. The PF08123B (Hitachi), a dual mode

(GSM, DCS) PA, is driven by a nominal power level of +3 dBm.

The PA has a single gain control line; the band to be used is

selected by applying either 0 V or 2 V to the PA’s VCTL input.

VAPC

VSET

VPOS

RFIN

COMM

FLTR

AD8311

52.3

+VS

2.7V

8-BIT

RAMP DAC

0V–2.55V

1R2, R3 OPTIONAL, SEE TEXT

1000pF

BAND

SELECT

0V/+2V

3.5V

1000pF

4.7 F

1000pF

POUT DCS

32dBm MAX

POUT GSM

35dBm MAX

LDC15D190A0007A

49.9

ATTN

20dB

PF08123B

VCTL

VAPC

(OPTIONAL,

SEE TEXT)

500

PIN GSM

3dBm

PIN DCS

3dBm

0.1

μF

R31

1.5k

150pF

R21

600

TO ANTENNA

Figure 31. Dual Mode (GSM/DCS) PA Control Example

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