LT7184SRVPBF datasheet(12/52 Pages) AD

12 / 52 page

Data Sheet

LT7184S

analog.com

Rev. 0

12 of 52

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Descriptions

Name

DESCRIPTION

PVIN0

Power Supply Input for Channel 0 and Internal LDO Regulators. This pin must be

bypassed to SGND as close as possible to the LT7184S, with a low ESR capacitor of value

4.7µF or more using the top PCB layer. If EXTVCC < 3V, then the internal LDO regulators

(for DRVCC, INTVCC, and VDD18) pull power from PVIN0.

SGND

Signal Ground. The return for the ITH0 and ITH1 compensation networks and the INTVCC

and VDD18 supply pins should be connected to an isolated ground return connected as

close as possible to the SGND pin. This pin is connected to PGND within the LT7184S

package. Do not connect the SGND isolated ground return to PGND in more than one

location in the application PCB. In PolyPhase applications the SGND and ITHN nodes

should be symmetrically connected to each IC in the PolyPhase configuration.

PVIN0

SGND

ITH0

ITH1

INTVCC

VDD18

VOUT0_CFG

DRVCC

PGND

PVIN1

27 SDA

28 SYNC

SW0

SW1

PGND

26 SCL

25 ALERT

24 FAULT0

23 FAULT1

22 SHARE_CLK

21 RUN1

20 RUN0

19 EXTVCC

LT7184S

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