Modulator Description

MC44BC373C/374C Technical Data

13.8 PLL Section

The reference divider is a fixed divide-by-128, resulting in a reference frequency of 31.25 KHz with a

4.0 MHz crystal. The 31.25 KHz reference frequency is used for both UHF and Sound PLLs.

The prescaler is a fixed divide-by-8 and is permanently engaged.

The programmable divider division-ratio is controlled by the state of control bits N0 to N11.

The divider-ratio N for a desired frequency F (in MHz) is given by:

with:

Programming a division-ratio N=0 is not allowed.

13.9 Logic Output Port

The LOP pin is used to control any logic function. The primary applications are to control an external

attenuator or an external switch, between the antenna input and TV output.

A typical attenuator application with PIN diode is shown. The LOP pin is used to switch the PIN

attenuator depending on the signal strength of the Antenna Input, thereby reducing the risks of

Intermodulation in certain areas. The LOP may also be used as an OFF position bypass switch or for other

logic functions in the application.

Figure 6. Attenuator Application with PIN Diode

13.10 Video Section - Peak White Clip

The modulator requires the following:

•

A composite video input with negative going sync pulses

•

A nominal level of 1Vp-p

This signal is AC-coupled to the video input where the sync tip level is clamped.

The video signal is then passed to a Peak White Clip circuit. The PWC circuit function is to soft-clip the

top of the video waveform if the “sync tip amplitude” to “peak white clip” goes too high. This method

avoids carrier over-modulation by the video. Clipping can be disabled by software.

N

F

8

---

128

4

---------

×

=

N

2048

N11

×

1024

N10

×…… 4 N2

×

2

N1

×

N0

++

+

+

+

=

LOP pin

Vcc

TV Out

Antenna

Input

Freescale Semiconductor, Inc.

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