 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TDA4AEN...Q1 数据表(PDF) 137 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TDA4AEN...Q1 数据表(HTML) 137 Page - Texas Instruments |
|
|
137 / 236 page  6.9.5.9.2 JTAG Table 6-52. JTAG Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.5 2.0 V/ns OUTPUT CONDITIONS CL Output load capacitance 5 15 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 83.5 1000(1) ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps (1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the additional trace delay. Table 6-53. JTAG Timing Requirements see Figure 6-41 NO. MIN MAX UNIT J1 tc(TCK) Cycle time minimum, TCK 40(1) ns J2 tw(TCKH) Pulse width minimum, TCK high 0.4P(2) ns J3 tw(TCKL) Pulse width minimum, TCK low 0.4P(2) ns J4 tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 2 ns tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 2 ns J5 th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 3 ns th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 3 ns (1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristis for the attached debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these assumptions. • Minimum TDO setup time of 2ns relative to the rising edge of TCK • TDI and TMS output delay in the range of -12.9ns to 13.9ns relative to the falling edge of TCK (2) P = TCK cycle time in ns Table 6-54. JTAG Switching Characteristics see Figure 6-41 NO. PARAMETER MIN MAX UNIT J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 12 ns TDO J2 J1 J4 TCK J5 TDI / TMS J3 J6 J7 J4 J5 Figure 6-41. JTAG Timing Requirements and Switching Characteristics www.ti.com TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 137 Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
