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TDA4AEN...Q1 数据表(PDF) 165 Page - Texas Instruments |
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TDA4AEN...Q1 数据表(HTML) 165 Page - Texas Instruments |
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165 / 236 page  6.9.5.16 MCASP Note McASP has one or more signals which can be multiplexed to more than one pin. Timing requirements and switching characteristics defined in this section are only valid for specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux Tool. Table 6-73, Table 6-74, Figure 6-62, Table 6-75, and Figure 6-63 present timing conditions, timing requirements, and switching characteristics for MCASP. Table 6-73. MCASP Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate 0.7 5 V/ns OUTPUT CONDITIONS CL Output load capacitance 1 10 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace 100 1100 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps Table 6-74. MCASP Timing Requirements see Figure 6-62 NO. MODE(1) MIN MAX UNIT ASP1 tc(AHCLKRX) Cycle time, MCASP[x]_AHCLKR/X(4) 20 ns ASP2 tw(AHCLKRX) Pulse duration, MCASP[x]_AHCLKR/X(4) high or low 0.5P(2) - 1.53 ns ASP3 tc(ACLKRX) Cycle time, MCASP[x]_ACLKR/X(4) 20 ns ASP4 tw(ACLKRX) Pulse duration, MCASP[x]_ACLKR/X(4) high or low 0.5R(3) - 1.53 ns ASP5 tsu(AFSRX-ACLKRX) Setup time, MCASP[x]_AFSR/X(4) input valid before MCASP[x]_ACLKR/X(4) ACLKR/X int 9.29 ns ACLKR/X ext in/out 4 ASP6 th(ACLKRX-AFSRX) Hold time, MCASP[x]_AFSR/X(4) input valid after MCASP[x]_ACLKR/X(4) ACLKR/X int -1 ns ACLKR/X ext in/out 1.6 ASP7 tsu(AXR-ACLKRX) Setup time, MCASP[x]_AXR(4) input valid before MCASP[x]_ACLKR/X(4) ACLKR/X int 9.29 ns ACLKR/X ext in/out 4 ASP8 th(ACLKRX-AXR) Hold time, MCASP[x]_AXR(4) input valid after MCASP[x]_ACLKR/X(4) ACLKR/X int -1 ns ACLKR/X ext in/out 1.6 (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. For details on AHCLKR/X clock source options, see the McASP Clocks table in the Multichannel Audio Serial Port (MCASP) section of the Module Integration chapter found in the Technical Reference Manual. (3) R = ACLKR/X period in ns. (4) x in MCASP[x]_* is 0, 1 or 2 www.ti.com TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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