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TDA4AEN...Q1 数据表(PDF) 167 Page - Texas Instruments |
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TDA4AEN...Q1 数据表(HTML) 167 Page - Texas Instruments |
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167 / 236 page  Table 6-75. MCASP Switching Characteristics see Figure 6-63 NO. PARAMETER DESCRIPTION MODE(1) MIN MAX UNIT ASP9 tc(AHCLKRX) Cycle time, MCASP[x]_AHCLKR/X(4) 20 ns ASP10 tw(AHCLKRX) Pulse duration, MCASP[x]_AHCLKR/X(4) high or low 0.5P(2) - 2 ns ASP11 tc(ACLKRX) Cycle time, MCASP[x]_ACLKR/X(4) 20 ns ASP12 tw(ACLKRX) Pulse duration, MCASP[x]_ACLKR/X(4) high or low 0.5R(3) - 2 ns ASP13 td(ACLKRX-AFSRX) Delay time, MCASP[x]_ACLKR/X(4) transmit edge to MCASP[x]_AFSR/X(4) output valid ACLKR/X int -1 7.25 ns ACLKR/X ext in/out -15.29 12.84 ASP14 td(ACLKX-AXR) Delay time, MCASP[x]_ACLKX(4) transmit edge to MCASP[x]_AXR(4) output valid ACLKR/X int -1 7.25 ns ACLKR/X ext in/out -15.29 12.84 ASP15 tdis(ACLKX-AXR) Disable time, MCASP[x]_ACLKX(4) transmit edge to MCASP[x]_AXR(4) output high impedance ACLKR/X int -1 7.25 ns ACLKR/X ext in/out -14.9 14 (1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0 ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1 ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1 ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0 ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1 (2) P = AHCLKR/X period in ns. For details on AHCLKR/X clock source options, see the McASP Clocks table in the Multichannel Audio Serial Port (MCASP) section of the Module Integration chapter found in the Technical Reference Manual. (3) R = ACLKR/X period in ns. (4) x in MCASP[x]_* is 0, 1 or 2 www.ti.com TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 167 Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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