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TDA4AEN...Q1 数据表(PDF) 171 Page - Texas Instruments |
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TDA4AEN...Q1 数据表(HTML) 171 Page - Texas Instruments |
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171 / 236 page  Table 6-78. MCSPI Switching Characteristics - Controller Mode see Figure 6-65 NO. PARAMETER MIN MAX UNIT SM1 tc(SPICLK) Cycle time, SPIn_CLK 20 ns SM2 tw(SPICLKL) Pulse duration, SPIn_CLK low 0.5P - 1 (1) ns SM3 tw(SPICLKH) Pulse duration, SPIn_CLK high 0.5P - 1 (1) ns SM6 td(SPICLK-PICO) Delay time, SPIn_CLK active edge to SPIn_D[x] -3 2.5 ns SM7 td(CS-PICO) Delay time, SPIn_CSi active edge to SPIn_D[x] 5 ns SM8 td(CS-SPICLK) Delay time, SPIn_CSi active to SPIn_CLK first edge PHA = 0 B - 4 (2) ns PHA = 1 A - 4 (3) ns SM9 td(SPICLK-CS) Delay time, SPIn_CLK last edge to SPIn_CSi inactive PHA = 0 A - 4 (4) ns PHA = 1 B - 4 (5) ns (1) P = SPIn_CLK period in ns. (2) T_ref is the period of the McSPI functional clock in ns. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register. • When Fratio = 1; B = (TCS(i) + 0.5) * T_ref. • When Fratio ≥ 2 and even value; B = (TCS(i) + 0.5) * Fratio * T_ref. • When Fratio ≥ 3 and odd value; B = ((TCS(i) * Fratio) + ((Fratio + 1) / 2 )) * T_ref. (3) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register. • When Fratio = 1; A = (TCS(i) + 1) * T_ref. • When Fratio ≥ 2 and even value; A = (TCS(i) + 0.5) * Fratio * T_ref. • When Fratio ≥ 3 and odd value; A = ((TCS(i) * Fratio) + ((Fratio - 1) / 2 )) * T_ref. (4) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register. • When Fratio = 1; A = (TCS(i) + 1) * T_ref. • When Fratio ≥ 2 and even value; A = (TCS(i) + 0.5) * Fratio * T_ref. • When Fratio ≥ 3 and odd value; A = ((TCS(i) * Fratio) + ((Fratio + 1) / 2 )) * T_ref. (5) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register. • When Fratio = 1; B = (TCS(i) + 0.5) * T_ref. • When Fratio ≥ 2 and even value; B = (TCS(i) + 0.5) * Fratio * T_ref. • When Fratio ≥ 3 and odd value; B = ((TCS(i) * Fratio) + ((Fratio - 1) / 2 )) * T_ref. www.ti.com TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 171 Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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