TDA4AEN...Q1 datasheet(176/236 Pages) TI

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6.9.5.18.1 MMC0 - eMMC Interface

MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the

following eMMC applications:

• Legacy SDR

• High Speed SDR

• High Speed DDR

• HS200

• HS400

Table 6-81 presents the required DLL software configuration settings for MMC0 timing modes.

Table 6-81. MMC0 DLL Delay Mapping for all Timing Modes

MMCSD0_SS_PHY_CTRL_x_REG

x = 4

x = 5

x = 1

BIT FIELD

[31:24]

[20]

[15:12]

[8]

[4:0]

[17:16]

[10:8]

[2:0]

[1]

BIT FIELD NAME

STRBSEL

OTAPDLYENA

OTAPDLYSEL

ITAPDLYENA

ITAPDLYSEL

SELDLYTXCLK

SELDLYRXCLK

FRQSEL

CLKBUFSEL

ENDLL

MODE

DESCRIPTION

STROBE

DELAY

OUTPUT

DELAY

ENABLE

OUTPUT

DELAY

VALUE

INPUT

DELAY

ENABLE

INPUT

DELAY

VALUE

DLL

DELAY CHAIN

SELECT

DLL REF

FREQUENCY

DELAY

BUFFER

DURATION

ENABLE

DLL

Legacy

SDR

8-bit PHY

operating 1.8V,

25MHz

0x0

0x1

0x10

0x3

NA(1)

0x7

0x0

High

Speed

SDR

8-bit PHY

operating 1.8V,

50MHz

0x0

0x1

0xA

0x3

NA(1)

0x7

0x0

High

Speed

DDR

8-bit PHY

operating 1.8V,

50MHz

0x0

0x1

0x6

0x1

0x3

0x0

0x4

NA(1)

0x1

HS200

8-bit PHY

operating 1.8V,

200MHz

0x0

0x1

0x8

0x1

Tuning(2)

0x0

NA(1)

0x1

HS400

8-bit PHY

operating 1.8V,

200MHz

0x77

0x1

0x5

0x1

Tuning(2)

0x0

NA(1)

0x1

(1)

NA means Not Applicable

(2)

Tuning means this mode requires a tuning algorithm to be used for optimal input timing

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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