TDA4AEN...Q1 datasheet(179/236 Pages) TI

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6.9.5.18.1.2 High Speed SDR Mode

Table 6-85, Figure 6-70, Table 6-86, and Figure 6-71 present timing requirements and switching characteristics

for MMC0 – High Speed SDR Mode.

Table 6-85. MMC0 Timing Requirements – High Speed SDR Mode

see Figure 6-70

NO.

Operating

Voltage

MIN

MAX

UNIT

HSSDR1

tsu(cmdV-clkH)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

1.8V

2.15

3.3V

2.24

HSSDR2

th(clkH-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

1.8V

1.27

3.3V

1.66

HSSDR3

tsu(dV-clkH)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge

1.8V

2.15

3.3V

2.24

HSSDR4

th(clkH-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge

1.8V

1.27

3.3V

1.66

Figure 6-70. MMC0 – High Speed SDR Mode – Receive Mode

Table 6-86. MMC0 Switching Characteristics – High Speed SDR Mode

see Figure 6-71

NO.

PARAMETER

Operating

Voltage

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

HSSDR5

tc(clk)

Cycle time, MMC0_CLK

HSSDR6

tw(clkH)

Pulse duration, MMC0_CLK high

9.2

HSSDR7

tw(clkL)

Pulse duration, MMC0_CLK low

9.2

HSSDR8

td(clkL-cmdV)

Delay time, MMC0_CLK falling edge to MMC0_CMD transition

1.8V

-1.55

3.05

3.3V

-1.8

2.2

HSSDR9

td(clkL-dV)

Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition

1.8V

-1.55

3.05

3.3V

-1.8

2.2

Figure 6-71. MMC0 – High Speed SDR Mode – Transmit Mode

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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