TDA4AEN...Q1 datasheet(189/236 Pages) TI

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6.9.5.18.2 MMC1/MMC2 - SD/SDIO Interface

MMC1/MMC2 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical

Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:

• Default speed

• High speed

• UHS–I SDR12

• UHS–I SDR25

• UHS–I SDR50

• UHS–I DDR50

• UHS–I SDR104

Table 6-99 presents the required DLL software configuration settings for MMC1/2 timing modes.

Table 6-99. MMC1/MMC2 DLL Delay Mapping for all Timing Modes

MMCSD1_SS_PHY_CTRL_4_REG/

MMCSD2_SS_PHY_CTRL_4_REG

MMCSD1_SS_PHY_CTRL_5_REG/

MMCSD2_SS_PHY_CTRL_5_REG

BIT FIELD

[20]

[15:12]

[8]

[4:0]

[2:0]

BIT FIELD NAME

OTAPDLYENA OTAPDLYSEL ITAPDLYENA

ITAPDLYSEL

CLKBUFSEL

MODE

DESCRIPTION

DELAY

ENABLE

DELAY

VALUE

INPUT

DELAY

ENABLE

INPUT

DELAY

VALUE

DELAY

BUFFER

DURATION

Default

Speed

4-bit PHY operating

3.3V, 25MHz

0x1

0x0

0x1

0x0

0x7

High

Speed

4-bit PHY operating

3.3V, 50MHz

0x1

0x0

0x1

0x0

0x7

UHS-I

SDR12

4-bit PHY operating

1.8V, 25MHz

0x1

0xF

0x1

0x0

0x7

UHS-I

SDR25

4-bit PHY operating

1.8V, 50MHz

0x1

0xF

0x1

0x0

0x7

UHS-I

SDR50

4-bit PHY operating

1.8V, 100MHz

0x1

0xC

0x1

Tuning(1)

0x7

UHS-I

DDR50

4-bit PHY operating

1.8V, 50MHz

0x1

0x9

0x1

Tuning(1)

0x7

UHS-I

SDR104

4-bit PHY operating

1.8V, 200MHz

0x1

0x6

0x1

Tuning(1)

0x7

(1)

Tuning means this mode requires a tuning algorithm to be used for optimal input timing

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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