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TDA4AEN...Q1 数据表(PDF) 192 Page - Texas Instruments |
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TDA4AEN...Q1 数据表(HTML) 192 Page - Texas Instruments |
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192 / 236 page  6.9.5.18.2.2 High Speed Mode Table 6-103, Figure 6-86, Table 6-104, and Figure 6-87 present timing requirements and switching characteristics for MMC1/MMC2 – High Speed Mode. Table 6-103. Timing Requirements for MMC1/MMC2 – High Speed Mode see Figure 6-86 NO. MIN MAX UNIT HS1 tsu(cmdV-clkH) Setup time, MMCx_CMD valid before MMCx_CLK rising edge 2.24 ns HS2 th(clkH-cmdV) Hold time, MMCx_CMD valid after MMCx_CLK rising edge 1.66 ns HS3 tsu(dV-clkH) Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge 2.24 ns HS4 th(clkH-dV) Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge 1.66 ns MMC[ ]_CLK x MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x H 1 S H 2 S H 3 S H 4 S Figure 6-86. MMC1/MMC2 – High Speed – Receive Mode Table 6-104. Switching Characteristics for MMC1/MMC2 – High Speed Mode see Figure 6-87 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMCx_CLK 50 MHz HS5 tc(clk) Cycle time. MMCx_CLK 20 ns HS6 tw(clkH) Pulse duration, MMCx_CLK high 9.2 ns HS7 tw(clkL) Pulse duration, MMCx_CLK low 9.2 ns HS8 td(clkL-cmdV) Delay time, MMCx_CLK falling edge to MMCx_CMD transition - 1.8 2.2 ns HS9 td(clkL-dV) Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition - 1.8 2.2 ns MMC[x]_CLK MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x H 5 S H 7 S H 8 S H 9 S HS6 Figure 6-87. MMC1/MMC2 – High Speed – Transmit Mode TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 192 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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