TDA4AEN...Q1 datasheet(217/236 Pages) TI

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8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines

The following section details the PCB routing guidelines that must be observed when connecting OSPI, QSPI, or

SPI devices.

8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback

• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device

• The signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to

B) must be ≤ 450ps (~7cm as stripline or ~8cm as microstrip)

• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached

OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal

propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)

• 50Ω PCB routing is recommended along with series terminations, as shown in Figure 8-1

• Propagation delays and matching:

– (A to B) ≤ 450ps

– (E to F, or F to E) = ((A to B) ± 60ps)

OSPI[x]_CLK

OSPI/QSPI/SPI

Device Clock Input

OSPI/QSPI/SPI

Device IO[y], CS#

OSPI[x]_D[y],

OSPI[x]_CSn[z]

OSPI_Board_01

OSPI[x]_LBCLKO

OSPI[x]_DQS

OSPI Device DQS

* 0Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.

Figure 8-1. OSPI Connectivity Schematic for No Loopback, Internal PHY Loopback, and Internal Pad

Loopback

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TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

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TDA4AEN...Q1 数据表(PDF) 217 Page - Texas Instruments