N

O

T

R

EC

O

M

M

EN

D

ED

FO

R

N

EW

D

ES

IG

N

S

La

st

Ti

m

e B

uy

: S

ept

. 200

6

N

o

Di

re

ct

Re

pl

ac

em

en

t

Al

te

rn

at

e

So

lu

tio

n:

FM

18

08

+F

M

40

05

FM3808

Rev. 1.3 (EOL)

Feb. 2006

Page 6 of 27

Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value

/M

Match: Setting this bit to 0 causes the Minutes value to be used in the alarm match. Setting this bit to 1

causes the match circuit to ignore the Minutes value.

7FF2h

Alarm – Seconds

D7

D6

D5

D4

D3

D2

D1

D0

M

10 sec.2

10 sec.1

10 sec.0

Seconds.3

Seconds.2

Seconds.1

Seconds.0

Contains the alarm value for the seconds and the mask bit to select or deselect the minutes value.

/M

Match: Setting this bit to 0 causes the Seconds value to be used in the alarm match. Setting this bit to1

causes the match circuit to ignore the Seconds value.

7FF1h

User-Nonvolatile

D7

D6

D5

D4

D3

D2

D1

D0

This register is an uncommitted nonvolatile register.

7FF0h

Flags/Control

D7

D6

D5

D4

D3

D2

D1

D0

WDF

AF

PF

CF

TST

CAL

W

R

WDF

Watchdog Timer Flag. This read-only bit is set to 1 when the watchdog timer is allowed to reach 0

without being reset by the user. It is cleared to 0 when the Flags/Control register is read.

AF

Alarm Flag. This read-only bit is set to 1 when the time and date match the values stored in the alarm

registers with the match bit(s) = 0. It is cleared when the Flags/Control register is read.

PF

Power-fail Flag. This read-only bit is set to 1 when power falls below the power-fail interrupt threshold

CF

Century Overflow Flag. This read-only bit is set to a 1 when the values in the years register overflows

from 99 to 00. This indicates a new century, such as going from 1999 to 2000 or 2099 to 2100. The user

should record the new century information as needed. This bit is cleared to 0 when the Flags/Control

register is read.

TST

Invokes factory test mode. Users should always set this bit to 0.

CAL

Calibration Mode. When set to 1, the clock enters calibration mode. When CAL is set to 0, the clock

operates normally.

W

Write Time. Setting the W bit to 1 freezes updates of the timekeeping registers. The user can then write

them with updated values. Setting the W bit to 0 causes the contents of the time registers to be

transferred to the timekeeping counters. This bit affects registers 7FF9h - 7FFFh.

R

Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a

holding register. The user can then read them without concerns over changing values causing system

errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 prior

to reading again. This bit affects registers 7FF9h - 7FFFh.

Real-Time Clock Operation

The real-time clock (RTC) consists of an oscillator, a

clock divider, and a register system to access the

information. It divides down the 32.768 kHz time-

base to provide the user timekeeping resolution of

one second (1Hz). The RTC will not run until the

oscillator is enabled. The ocillator enable bit is bit 7

of register 7FF8h and is automatically set to a one

(disabled) when the device powers up without a

backup supply.

Static registers provide the user with read/write

access to the time values. The synchronization of

these registers with the timekeeper core is performed

using R and W bits in register 7FF0h. Setting the R

bit from 0 to 1 causes a transfer of the timekeeping

information to holding registers that can be read by

the user. If a timekeeper update is in progress when

the R is set, the update will be completed prior to

loading the registers. Another update cannot be

performed unless the R bit is first cleared to 0 again.

Setting the W bit causes the timekeeper to freeze

updates. Clearing it to 0 causes the values in the time

registers to be written into the timekeeper core. Users

should be sure not to load invalid values, such as FFh

to any of the timekeeping registers.

Updates to the timekeeping core occur continuously

except when frozen. A diagram of the timekeeping

core is shown in Figure 2.

Backup Power

The

real-time

clock/calendar

is

intended

for

permanently

powered

operation.

When

primary