FM3808_06 datasheet(17/27 Pages) RAMTRON

17 / 27 page

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FM3808

Rev. 1.3 (EOL)

Feb. 2006

Page 17 of 27

FRAM Design Considerations

SRAM and FRAM alike begin each read/write cycle

with a new address being driven prior to the chip

enable transition low. The falling edge of chip enable

latches the address and a memory access starts. For

subsequent memory accesses, SRAMs allow /CE to

remain low while the address bus changes. FRAM

devices do not allow this signalling. Every FRAM

access requires a falling edge of /CE, therefore users

cannot ground this pin as you might with SRAM.

Users who are modifying existing designs to use

FRAM should examine the memory controller for

timing compatibility of address and control pins.

Each memory access must be qualified with a low

transition of /CE. In many cases, this is the only

change

required.

example

the

signal

relationships is shown in Figure 8 below. Also shown

is a common SRAM signal relationship that will not

work for the FRAM devices.

The reason for /CE to strobe for each address is two-

fold: it latches the new address and creates the

necessary precharge period while /CE is high.

Address 1

Address 2

Data 1

Data 2

Valid Memory Signaling Relationship

Address

Data

FRAM

signaling

Address 2

Data 1

Address

Data

SRAM

signaling

Invalid Memory Signaling Relationship

Address 1

Data 2

Figure 8. Memory Address and /CE Relationships

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