PPC405GP-3EE266C datasheet(42/59 Pages) AMCC

42 / 59 page

405GP – Power PC 405GP Embedded Processor

AMCC

Revision 2.03 – September 7, 2007

Data Sheet

[TS3:6]GPIO5:8

Trace status. To access this function, software must toggle a DCR bit

General Purpose I/O.

O[I/O]

5V tolerant

3.3V LVTTL

[TrcClk]GPIO9

Trace interface clock. A toggling signal that is always half of the CPU

core frequency. To access this function, software must toggle a DCR

bit

General Purpose I/O.

O[I/O]

5V tolerant

3.3V LVTTL

Ground pins

GND

Ground

Note: On the 456-ball packages, L11-L16, M11-M16, N11-N16, P11-

P16, R11-R16, and T11-T16 are also thermal balls.

On the 413-ball package, J11, J13, K11-K13, L11-L13, M11-

N13, N11-N13, P11-P13, R11, and R13 are also thermal balls.

OVDD pins

OVDD

Output driver voltage—3.3V.

VDD pins

VDD

Logic voltage—2.5V.

Other pins

Reserved

Reserved—Except for Y5 (on the 413-ball package) or AF4, do not

connect signals, voltage, or ground to these pins. Y5 (on the 413-ball

package) and AF4 must be tied to OVDD or GND.

Signal Functional Description (Part 8 of 8)

Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.

Notes:

1. Receiver input has hysteresis.

2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.

3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 34 for recommended termination values.

4. If not used, must pull up.

5. If not used, must pull down.

6. Strapping input during reset; pull up or pull down as required.

7. Pull-up may be required. See “External Bus Control Signals” on page 34.

Signal Name

Description

I/O

Type

Notes

PPC405GP-3EE266C 数据表(PDF) 42 Page - Applied Micro Circuits Corporation

PPC405GP-3EE266C 数据表(HTML) 42 Page - Applied Micro Circuits Corporation

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