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PPC405GP-3EE266C 数据表(PDF) 53 Page - Applied Micro Circuits Corporation

部件名 PPC405GP-3EE266C
功能描述  Power PC 405GP Embedded Processor
PDF  59 Pages
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制造商  AMCC [Applied Micro Circuits Corporation]
网页  http://www.amcc.com
标志 AMCC - Applied Micro Circuits Corporation

PPC405GP-3EE266C 数据表(HTML) 53 Page - Applied Micro Circuits Corporation

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405GP – Power PC 405GP Embedded Processor
AMCC
53
Revision 2.03 – September 7, 2007
Data Sheet
I/O Specifications—133 and 200MHz
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
command is used by SDRAM.
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
SDRAM Interface
BA1:0
na
na
7.5
1
19
12
MemClkOut
1, 2
BankSel3:0
na
na
6.2
1
19
12
MemClkOut
2
CAS
na
na
7.5
1
19
12
MemClkOut
1, 2
ClkEn0:1
na
na
5.2
1
40
25
MemClkOut
2
DQM0:3
na
na
6.1
1
19
12
MemClkOut
2
DQMCB
na
na
6.2
1
19
12
MemClkOut
2
ECC0:7
2
1
6.2
1
19
12
MemClkOut
2
MemAddr12:0
na
na
7.6
1
19
12
MemClkOut
1, 2
MemData0:31
2
1
6.3
1
19
12
MemClkOut
2
RAS
na
na
7.5
1
19
12
MemClkOut
1, 2
WE
na
na
7.5
1
19
12
MemClkOut
1, 2
External Slave Peripheral Interface
DMAAck0:3
na
na
8
0
12
8
PerClk
DMAReq0:3
5
1
na
na
na
na
PerClk
EOT0:3/TC0:3
dc
dc
8
0
12
8
PerClk
PerAddr0:31
4
1
10
0
19
12
PerClk
PerBLast
4
1
8
0
12
8
PerClk
PerCS0
PerCS1:7[GPIO10:16]
na
na
8
0
12
8
PerClk
PerData0:31
6
1
10
0
19
12
PerClk
PerOE
na
na
8
0
12
8
PerClk
PerPar0:3
4
1
10
0
19
12
PerClk
PerR/W
4
1
8
0
12
8
PerClk
PerReady
9
1
na
na
na
na
PerClk
PerWBE0:3
3
1
8
0
12
8
PerClk
External Master Peripheral Interface
BusReq
na
na
8
0
12
8
PerClk
ExtAck
na
na
7
0
12
8
PerClk
ExtReq
5
1
na
na
na
na
PerClk
ExtReset
na
na
8
0
19
12
PerClk
HoldAck
na
na
8
0
12
8
PerClk
HoldPri
4
1
nana
nana
PerClk
HoldReq
5
1
na
na
na
na
PerClk
PerClk
na
na
0.9
0.7
19
12
PLB Clk
4
PerErr
3
1
na
na
na
na
PerClk



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