TAS5815PWPR datasheet(49/123 Pages) TI

49 / 123 page

7.5.3.3 Protection and Monitoring

7.5.3.3.1 Overcurrent Shutdown (OCSD)

Under severe short-circuit event, such as a short to PVDD or ground, the device uses a peak-current detector,

and the affected channel shuts down in < 100ns if the peak current are enough. The shutdown speed depends

on a number of factors, such as the impedance of the short circuit, supply voltage, and switching frequency. The

user may restart the affected channel via I2C. An OCSD event activates the fault pin, and the I2C fault register

saves a record. If the supply or ground short is strong enough to exceed the peak current threshold but not

severe enough to trigger the OCSD, the peak current limiter prevents excess current from damaging the output

FETs, and operation returns to normal after the short is removed.

7.5.3.3.2 DC Detect

If the TAS5815 device measures a DC offset in the output voltage, the ADR/ FAULT line is pulled low and the

OUTxx outputs transition to high impedance, signifying a fault.

7.5.3.3.3 Device Over Temperature Protection

Once the die temperature exceed 160°C (Typical), device will set the output driver from Play mode to Hi-Z Mode.

Over temperature shutdown fault reported by GLOBAL_FAULT2 (0x72) register in Book0/Page0. Set this fault's

behavior to Auto-recovery mode, device will come back to play mode automatically once the die temperature

drop down to 150°C or device needs re-enter into play mode by clearing fault with FAULT_CLEAR (0x78)

7.5.3.3.4 Over Voltage Protection

Once the PVDD voltage exceeds the OVETHRES(PVDD), device will set the output driver from Play mode to Hi-Z

mode. Over voltage fault reported by GLOBAL_FAULT1 (0x71) register in Book0/Page0. Once PVDD voltage

returns to normal, device will come back to Play mode. But this bit still keeps 1 unless clear it by FAULT_CLEAR

(0x78) register in Book0/Page0 manually.

7.5.3.3.5 Under Voltage Protection

Once the PVDD voltage drop below the UVETHRES(PVDD) (4 V Typical), device will set the output driver from Play

mode to Hi-Z mode. Under voltage fault reported by GLOBAL_FAULT1 (0x71) register in Book0/Page0. Once

PVDD rise above 4.25 V (Typical), device will come back to Play mode. But this bit still keeps 1 unless clear it by

FAULT_CLEAR (0x78) register in Book0/Page0 manually.

7.5.3.3.6 Clock Fault

Once there has any Clock error occurs (Clock Halt, SCLK/LRCLK Ratio Error, Pll unlock, FS error) , Section

8.1.12 and Section 8.1.14 monitor these errors and real-time report with details, device will enter into Hi-Z mode.

Clock Fault reported in Section 8.1.35 in Book0/Page0. Once the clock error been removed, device will come

back to play mode automatically. But this bit still keeps 1 unless clear it by Section 8.1.41 in Book0/Page0

manually.

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TAS5815

SLOSEA8 – DECEMBER 2024

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