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TAS5815PWPR 数据表(PDF) 53 Page - Texas Instruments |
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TAS5815PWPR 数据表(HTML) 53 Page - Texas Instruments |
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53 / 123 page  8.1.1 RESET_CTRL Register (Offset = 1h) [Reset = 00h] RESET_CTRL is shown in Figure 8-1 and described in Table 8-3. Return to the Summary Table. Reset control Figure 8-1. RESET_CTRL Register 7 6 5 4 3 2 1 0 RESERVED RST_MOD RESERVED RST_REG W-0h W-0h W-0h W-0h Table 8-3. RESET_CTRL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED W 0h 4 RST_MOD W 0h WRITE CLEAR BIT Reset Modules This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit is auto cleared and can be set only in hiz mode. 0: Normal 1: Reset modules 3-1 RESERVED W 0h 0 RST_REG W 0h WRITE CLEAR BIT Reset Registers This bit resets the mode registers back to their initial values. The RAM content is not cleared. This bit is auto cleared and must be set only when the DAC is in hiz mode (resetting registers when the DAC is running is prohibited and not supported) 0: Normal 1: Reset mode registers www.ti.com TAS5815 SLOSEA8 – DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: TAS5815 |
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