SC1480AEVB datasheet(9/23 Pages) SEMTECH

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 2003 Semtech Corp.

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SC1480A

POWER MANAGEMENT

Applications Information (Cont.)

allows switching to occur, if enabled (see below). When

RE.IN rises above the RE.IN threshold, RE.OUT will start

to rise. The switching controller is enabled by two things:

RE.IN being greater than the RE.IN threshold and VDDP

being greater than the VDDP UVLO of 3.3V, above which

switching will commence (assuming VCCA is present).

Switching always starts with DL to charge up the BST

capacitor. With the softstart circuit (automatically)

enabled, the SC1480A will progressively limit the VTT

output current (by limiting the current out of the ILIM pin)

over a predetermined time period of 440 switching cycles.

The ramp occurs in four steps:

1) 110 cycles at 25% ILIM with double minimum off-time

2) 110 cycles at 50% ILIM with normal minimum off-time

3) 110 cycles at 75% ILIM with normal minimum off-time

4) 110 cycles at 100% ILIM with normal minimum

off-time. At this point the output undervoltage and power

good circuitry is enabled.

If VDDP falls below 3.5V (nom.) the VTT regulator will

shut down. If RE.IN falls below the RE.IN threshold,

RE.OUT and VTT will shut down. There is 100mV of

hysteresis built into the VCCA UVLO circuit and when VCCA

falls to 4.1V (nom.) the output drivers are shut down and

tristated and the RE.OUT buffer shut down and disabled.

MOS.ET Gate Drivers

The DH and DL drivers are optimized for driving

moderate-sized high-side, and larger low-side power

MOS.ETs. An adaptive dead-time circuit monitors the DL

output and prevents the high-side MOS.ET from turning

on until DL is fully off (below ~1V). Conversely, it

monitors the phase node, LX, to determine the state of

the high side MOS.ET, and prevents the low-side MOS.ET

from turning on until DH is fully off (LX below ~1V). Be

sure there is low resistance and low inductance between

the DH and DL outputs to the gate of each MOS.ET.

DDR Reference Buffer

The reference buffer is capable of driving 3mA and sinking

25µA. Since the output is class A, if additional sinking is

required an external pulldown resistor can be added.

Make sure that the ground side of this pulldown is tied

to VSSA. As with most opamps, a small resistor is required

when driving a capacitive load. To ensure stability use

either a 10Ω resistor in series with a 1µ. capacitor or a

100Ω resistor in series with a 0.1µ. capacitor from

RE.OUT to VSSA.

Since it is possible to have as much as 10µ. to 20µ. of

capacitance at the memory socket or on-board the

DIMMs, it is recommended that a 0Ω resistor is placed

between RE.OUT and the DIMM sockets. This allows the

addition of extra resistance between RE.OUT and the

DIMMs to avoid spurious OVP at startup, which can occur

if RE.OUT rises really slowly and VTT overshoots it. The

extra resistance allows RE.OUT to rise faster, avoiding

this issue.

RE.IN should also be filtered so that VDDQ ripple does

not appear at the RE.IN pin. If a resistor divider is used

to create RE.IN from VDDQ, then a 0.1µ. capacitor from

RE.IN to VSSA will provide adequate filtering.

VTT Dropout Performance

The output voltage adjust range for continuous-

conduction operation is limited by the fixed 550ns

(maximum) minimum off-time one-shot. .or best dropout

performance, use the slowest on-time setting of 200kHz.

When working with low input voltages, the duty-factor

limit must be calculated using worst-case values for on

and off times. The IC duty-factor limitation is given by:

)

MAX

(

OFF

)

MIN

(

)

MIN

(

DUTY

Be sure to include inductor resistance and MOS.ET on-

state voltage drops when performing worst-case dropout

duty-factor calculations.

SC1480A System DC Accuracy (VTT)

Two IC parameters effect system DC accuracy, the error

comparator offset voltage, and the switching frequency

variation with line and load. The SC1480A regulates to

the RE.OUT voltage not the RE.IN voltage. Since DDR

specifications are written with respect to RE.OUT, the

offset of the reference buffer does not create a regulation

error.

The error comparator offset does not drift significantly

with supply and temperature. Thus, the error comparator

contributes 1% or less to DC system inaccuracy.

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