3

HV57708

Symbol

Parameter

Min

Max

Units

Conditions

I

DD

V

-

15

mA

V

I

PP

High voltage supply current

-

100

µA

Outputs high

-

100

µA

Outputs low

I

DDQ

Quiescent V

-

100

µA

All V

V

OH

High level output

HV

OUT

65

-

V

I

D

OUT

V

-

V

I

V

OL

Low level output

HV

OUT

-

7.0

V

I

D

OUT

-

0.5

V

I

I

IH

High-level logic input current

-

1.0

µA

V

I

IL

Low-level logic input current

-

-1.0

µA

V

V

OC

High voltage clamp diode

-

1.0

V

I

Logic signal inputs and Data inputs have t

Symbol

Parameter

Min

Max

Units

Conditions

f

CLK

Clock frequency

-

8

MHz

Per register

t

Clock width high or low

62

-

ns

---

t

SU

Data set-up time before clock rises

10

-

ns

---

t

H

Data hold time after clock rises

15

-

ns

---

t

Time from latch enable to HV

OUT

-

500

ns

C

t

DHL

Delay time clock to data high to low

-

70

ns

C

t

DLH

Delay time clock to data low to high

-

70

ns

C

t

Delay time clock to LE low to high

25

-

ns

---

t

WLE

LE pulse width

25

-

ns

---

t

SLE

LE set-up time before clock rises

0

-

ns

---

* t

output to stabilize).