SH3003 datasheet(12/30 Pages) SEMTECH

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SH3003

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- DRAFT

POWER MANAGEMENT

The second circuit for supervising the processor is the

watchdog timer. Whereas the low VDD/Brownout Detector

monitors supply voltage, the watchdog timer monitors be-

havior. It is based on a programmable timer that must be

restarted periodically by the host micro. If software fails

to restart the timer, the watchdog resets the processor.

Restarting the timer takes considerable processing, mak-

ing it unlikely that it would occur accidentally, as might

happen for a simple pin-strobe conﬁguration of typical

watchdog IC.

The watchdog is disabled after reset occurs. It stays dis-

abled until initialized by the host processor. The initializa-

tion requires the watchdog clock mode to be selected (see

Figure 1) and the 7-bit time-out value to be set. As soon

as the time-out is written, the watchdog begins operations

and can not be stopped; also, the time-out value and or

clock source can no longer be changed.

The two clock sources available for the watchdog are the

internal 32.768kHz clock and the CLKOUT signal. When

operating from the 32.768kHz source, the time-out inter-

val is programmable from 7.8125ms to one second with

resolution of 7.8125ms. The internal 32.768kHz clock is

running all the time, therefore the time-out duration is

ﬁxed and predictable.

When operating from the CLKOUT signal the time-interval is

programmable between 256 and 32768 cycles of CLKOUT

with resolution of 256 cycles. The actual time-out duration

is variable and depends both on the frequency of CLKOUT

signal and the amount of time target micro spends in the

STOP mode, when the CLKOUT signal is also stopped.

These two clock modes, together with the programmable

time-out value, allow the SH3003 exceptional ﬂexibility,

previously unattainable by existing discrete watchdog so-

lutions.

The watchdog timer is kept from timing out by periodic

reload of the time-out value, triggered by a write of a code

byte to the Watchdog Reload Register. As a further safety

measure, there are two different and alternating code

bytes that should be written to the same Watchdog Re-

load Register. The code values are 0x5A and 0xC3. The

timer is reloaded after every write of a single code byte.

The code byte should be written to the Watchdog Reload

expires. Also, reset is initiated immediately if the value of

the code byte is incorrect or out of sequence. When the

watchdog triggers the reset, its duration is 12ms.

Using two separate software routines, each to write one of

the code values, results in the highest level of system se-

curity. These routines must execute in the correct order. It

is unlikely that runaway code could manage this. In addi-

tion, this design makes it difﬁcult for the code to become

stuck in a tight loop resetting the watchdog.

Application Information (continued)

Watchdog Timer

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