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 2005 Semtech Corp.

www.semtech.com

SC1485

POWER MANAGEMENT

Key points for the power section:

1) there should be a very small input loop, well decoupled.

2) the phase node should be a large copper pour, but compact since this is the noisiest node.

3) input power ground and output power ground should not connect directly, but through the ground planes instead.

4) The two outputs should not share their input capacitors, and these should have separate PWR_SRC and PGND

(component-side) copper pours.

5) The two output inductors should not be placed adjacent to each other to avoid crosstalk.

6) Notice in Figure 13 placement of 0

Ω resistor at the bottom of the output capacitor to connect to VSSA1/2 for

each output.

Connecting the control and power sections should be accomplished as follows (see Figure 14 below):

1) Route VSSA1/2 and their related feedback traces as differential pairs routed in a “quiet” layer away from noise

sources.

2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces

with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,

with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power

ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high

frequencies, thus should be kept as short as practical. DH has LX as its return path.

3) BST is also a noisy node and should be kept as short as possible.

4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the

ground plane.

5) Locate the current limit sense resistors between the LX and ILIM pins at the device.

0402

EN/PSV1

22

TON1

23

VOUT1

24

VCCA1

25

FB1

26

PGD1

27

VSSA1

28

PGND1

1

DL1

2

VDDP1

3

ILIM1

4

LX1

5

DH1

6

BST1

7

EN/PSV2

8

TON2

9

VOUT2

10

VCCA2

11

FB2

12

PGD2

13

VSSA2

14

PGND2

15

DL2

16

VDDP2

17

ILIM2

18

LX2

19

DH2

20

BST2

21

U1

SC1485

Q2

Q1

R5

L1

0402

Q3

IRF7811AV

Q4

FDS6676S

R10 7k87

L2

2u2

Figure 14: Connecting Control and Power Sections

Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node

traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.