SN74LS74A

4

Figure 1. Clock to Output Delays, Data

Set-Up and Hold Times, Clock Pulse Width

AC WAVEFORMS

*The shaded areas indicate when the input is permitted to change for predictable output performance.

D*

CP

Q

Q

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

tPLH

tPHL

tPLH

tPHL

th(L)

ts(L)

tW(H)

tW(L)

ts(H)

th(H)

1

fMAX

1.3 V

Figure 2. Set and Clear to Output Delays,

Set and Clear Pulse Widths

tW

1.3 V

1.3 V

tW

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

tPLH

tPHL

tPLH

tPHL

SET

CLEAR

Q

Q

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