Dual D-Type Positive

Edge-Triggered Flip-Flop

The SN74LS74A dual edge-triggered flip-flop utilizes Schottky

TTL circuitry to produce high speed D-type flip-flops. Each flip-flop

has individual clear and set inputs, and also complementary Q and Q

outputs.

Information at input D is transferred to the Q output on the

positive-going edge of the clock pulse. Clock triggering occurs at a

voltage level of the clock pulse and is not directly related to the

transition time of the positive-going pulse. When the clock input is at

either the HIGH or the LOW level, the D input signal has no effect.

MODE SELECT – TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

OPERATING MODE

SD

SD

D

Q

Q

Set

Reset (Clear)

*Undetermined

Load “1” (Set)

Load “0” (Reset)

L

H

L

H

H

H

L

L

H

H

X

X

X

h

l

H

L

H

H

L

L

H

H

L

H

*

Both outputs will be HIGH while both SD and CD are LOW, but the output

states are unpredictable if SD and CD go HIGH simultaneously. If the levels

at the set and clear are near VIL maximum then we cannot guarantee to meet

the minimum level for VOH.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input

i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition.

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

4.75

5.0

5.25

V

TA

Operating Ambient

Temperature Range

0

25

70

°C

IOH

Output Current – High

– 0.4

mA

IOL

Output Current – Low

8.0

mA

LOW

POWER

SCHOTTKY

Device

Package

Shipping

ORDERING INFORMATION

SN74LS74AN

14 Pin DIP

2000 Units/Box

SN74LS74AD

14 Pin

SOIC

D SUFFIX

CASE 751A

2500/Tape & Reel

PLASTIC

N SUFFIX

CASE 646

14

1

14

1

74LS74

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