HT82K96E datasheet(13/44 Pages) HOLTEK

13 / 44 page

HT82K96E

Rev. 2.00

October 11, 2007

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a

²warm re -

set

² that resets only the Program Counter and SP, leav-

ing the other circuits in their original state. Some regis-

ters remain unchanged during other reset conditions.

Most registers are reset to the

²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

WDT time-out during normal operation

WDT wake-up HALT

Note:

²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer/event Counter

Off

Input/output Ports

Input mode

Stack Pointer

Points to the top of the stack

V D D

R E S

Reset Circuit

W a r m R e s e t

W D T

H A L T

C o l d

R e s e t

R E S

S y s t e m R e s e t

S S T

1 0 - b i t R i p p l e

C o u n t e r

O S C 1

Reset Configuration

t S S T

R E S

V D D

S S T T i m e - o u t

C h i p R e s e t

Reset Timing Chart

HT82K96E 数据表(PDF) 13 Page - Holtek Semiconductor Inc

HT82K96E 数据表(HTML) 13 Page - Holtek Semiconductor Inc

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HT82K96E 数据表(PDF) 13 Page - Holtek Semiconductor Inc

HT82K96E 数据表(HTML) 13 Page - Holtek Semiconductor Inc

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