HT82K96E

Rev. 2.00

21

October 11, 2007

SIES. Register (for version C or later version) is used to indicate the present signal state which the SIE receives and

also defines whether the SIE has to change the device address automatically.

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Func.

Reserved bit

F0_ERR

Adr_set

R/W

R/W

R/W

Reg_Adr

01000101B

Note: Bit7 must be

²0²

Func. Name

R/W

Description

R/W

This bit is used to configure the SIE to automatically change the device address with

the value of the Address+Remote_WakeUp Register (42H).

When this bit is set to

²1² by F/W, the SIE will update the device address with the value

of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully

read the data from the device by the IN operation. The SIE will clear the bit after updat-

ing the device address. Otherwise, when this bit is cleared to

²0², the SIE will update

the device address immediately after an address is written to the Address+Re-

mote_WakeUp Register (42H)

Default 0

F0_Err

R/W

This bit is used to indicate that some errors have occurred when accessing the FIFO0.

This bit is set by SIE and cleared by F/W.

Default 0

SIES (45H) Register Table

MISC register combines a command and status to control desired endpoint FIFO action and to show the status of

wanted endpoint FIFO. The MISC will be cleared by USB reset signal.

Bit No.

Label

R/W

Function

0

REQ

R/W

After setting other status of desired one in the MISC, endpoint FIFO can be requested

by setting this bit to

²1². After job has been done, this bit has to be cleared to ²0²

1

TX

R/W

This bit defines the direction of data transferring between MCU and endpoint FIFO.

When the TX is set to

²1², this means that MCU wants to write data to endpoint FIFO.

After the job has been done, this bit has to be cleared to

²0² before terminating re-

quest to represent end of transferring. For reading action, this bit has to be cleared to

²0² to represent that MCU wants to read data from endpoint FIFO and has to be set to

²1² after the job done.

2

CLEAR

R/W Clear the requested endpoint FIFO, even the endpoint FIFO is not ready.

4

3

SELP1

SELP0

R/W

To define which endpoint FIFO is selected, SELP1,SELP0:

00: endpoint FIFO0

01: endpoint FIFO1

10: endpoint FIFO2

11: endpoint FIFO3

5

SCMD

R/W

It is used to show that the data in endpoint FIFO is SETUP command. This bit has to

be cleared by firmware. That is to say, even the MCU is busing, the device will not

miss any SETUP commands from host.

6

READY

R

Read only status bit, this bit is used to indicate that the desired endpoint FIFO is ready

to work.

7

LEN0

R/W

It is used to indicate that a 0-sized packet is sent from host to MCU. This bit should be

cleared by firmware.

MISC (46H) Register