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POWER MANAGEMENT

SC2434

Phase Current Balance

One of the fundamental challenges for multi-phase solu-

tions is to balance the phase currents to achieve the best

possible electrical and thermal performance. It is quite

easy to use the SC2434 control topology to achieve very

good phase current balance. Since the current of all the

phases passes through the same current sensing compo-

nent and the same current current of all the phases are

well balanced on pulse by pulse basis. This control results

in small and even output voltage ripple and evenly distrib-

uted thermal load. Additional advantages of using input

current mode are less sensing circuitry, less IC pins, and

less power loss on the sensing resistor comparing sensing

inductor current on the output side. Fig. 2 shows the wave-

form of inductor currents under heavy load conditions,

which clearly demonstrates the excellent performance of

SC2434 on balancing the phase current.

Applications Information (Cont.)

voltage. Fig. 3 shows the measured waveforms of power

up and power down.

Fig. 3 - Shows the measured waveforms of power up and power

down.

Over Current Protection (OCP)

When sensed current signal across the differential input

of the current amplifier exceeds 120mV typical value, OCP

circuitry will pull down the error amplifier output voltage

and also discharge the soft start capacitor. The pull down

of the error amplifier will not be released until the soft

capacitor is discharged bellow 0.3V. At this point, the

PWM outputs are reactivated and the soft start capacitor

begins to charge up again through the internal 6 Kohm

resistor. The VR will try to bring up the output voltage until

the over load or short circuit condition is removed. The

hiccup mode OCP can significantly reduce the average out-

put current under overload conditions. The hiccup timing

is controlled by the soft start time constant. Please also

notice that the OCP threshold has less than 10% toler-

ance, hence, the onset of the OCP is quite accurate. The

advantage is that the VR designer does not need to re-

serve big thermal headroom to deal with the worst-case

operation when load is over 100% but the OCP has yet not

been triggered. An RC filter is needed to filter out the

leading edge voltage spike across the current sensing re-

sistor to prevent false triggering of the OCP. The time con-

stant should be around 200nS (please see application

schematic).

Power Good

SC2434 features a power good input and an open collec-

tor power good output. The VR output voltage is scaled

down through a resistive divider and this signal is fed into

PGIN (power good input) pin. The scaled VR output volt-

age has to be bigger than 0.8V otherwise the power good

output pin is pulled down. A 5 Kohm pull-up resistor and

a 0.1uF capacitor to ground are recommended to prevent

false trigger during logic transition.

Fig. 2 - Measured inductor currents of SC2434 3-phase VR

under heavy load condition.

Under Voltage Lockout (UVLO)

During power up, when UVLO circuitry detects the chip

supply (Vcc) be bigger than 7.5V (typical value with proper

hysteresis), the bandgap voltage reference starts to charge

the external soft start capacitor through a 6 Kohm inter-

nal resistor. When soft start capacitor voltage reaches

0.5V, the output voltage starts to build up which follows

the exponential voltage profile of the soft start capacitor.

The soft start process ensures that the output voltage will

have no over shoot. During power down, UVLO will dis-

charge the soft start capacitor to shut of the PWM. The

load will absorb the energy in the output filter and no reso-

nance will occur. Hence, the CPU will not see any negative

Output

voltage

Output

voltage

Input

voltage

Input

voltage