9

 2005 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC2434

be caused by layout inductances, may alter the PWM

comparator trip point. The value of R

adjusted to compensate for such parasitic effects.

It must be noted that the current amplifier gain is quite

precise, with greater than 80dB of Common Mode

Rejection Ratio (CMRR). Thus the droop accuracy is

primarily based upon external components tolerances. By

employing 1% current sensing element with very low

temperature coefficient, this topology is proved to be the

best comparing the schemes of using R

using inductor winding resistance sensing. The accurate

drooping translates into minimum amount output bulk

capacitor needed to meet the voltage regulation specifica-

tions and the least system cost.

Programming The DC Level Of The Output Voltage

Kirchoff’s current law can be applied to the error

amplifier’s inverting input (see Fig. 1) to calculate R

the DC level setting resistor. For given output voltage set

point and VID setting, the resistance can be calculated

by:

Applications Information (Cont.)

H p_ccm sR

,

()

G pwm

1s C

. R

c

.

1s R

. C

.

(

) 1

1.5

s

π F

s

.

.

s

π F

s

.

2

.

.

Fig. 4 - Loop gain and compensation of the current mode

con-

troller.

where C

error amplifier output and the inverting input with a value

of 11pF.

The power stage transfer function under continuous

conduction mode can be approximated by:

where N

highest set point (VID=00000). For example, when VID

[4:1]=00100, N

V

output voltage and, as a first approximation, it is equal to

1..7V. Again, V

The final value of R

experimentally after the droop resistor has been chosen.

Control Loop Compensation

The current mode control yields a power supply easy to

compensate because the power stage has first order (single

pole) behavior. The SC2434 provides internal slope

compensation to avoid sub harmonic oscillation of the

current loop. The added ramp signal has 300mV peak-to-

peak amplitude and the ramp frequency is as same as

the oscillator frequency.

As depicted in Fig. 4, the gain for the voltage feedback

loop can be expressed as a product of the power stage

gain and the compensator gain:

Loop s R

,

()

H p_ccm sR

,

() H c s

()

.

0

-

+

Err_A mp

Verror

Loop G ain

Copam

Ccomp

Rcomp

-1

Ccomp

1/(R*C)

Rdrp

POWER

STAGE

Rdrp/R fb

Vin/( VR*N phas e)

-1

Power St age

Compensator

1/(E SRC)

Pol e

Fsw/2

Zero

0dB

Fsw/2

-2

-2

1/(R*C)

Vout

where G

The power stage has an ESR zero, a dominant pole at

low frequency, and a pair of complex pole located at one

half of the switching frequency. The parameter used here

are defined as below:

C = output bulk capacitance

R = load resistance

R

F

The PWM gain is defined as:

R os

V bg

V set V bg

R FB

V eo V bg

R drp

N DAC_STEP I DAC_LSB

.

G pw m

R ! N

R

phas e

se n se · G CA