QST108

Electrical characteristics

35/38

6.8

protocol described in the following table with the restriction mentioned below:

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (SDA and SCL).

Figure 19.

Table 29.

I²C characteristics

Symbol

Parameter

Standard mode

Fast mode

Unit

1.

Max. (1)

Min. (1)

Max. (1)

SCL clock low time

4.7

1.3

µs

SCL clock high time

4.0

0.6

SDA setup time

250

100

ns

SDA data hold time

0 (3)

2.

The device must internally proivde a hold time of at least 300ns for the SDA signal in order to bridge the

undefined region of the falling esdge of the SCL signal.

3.

The maximum hold time of the START condition has only to be met if the interface does not stretch the low

period of the SCL signal.

SDA and SCL rise time

1000

300

ns

SDA and SCL fall time

300

300

START condition hold time

4.0

0.6

µs

Repeated START condition setup time

4.7

0.6

STOP condition setup time

4.0

0.6

μs

4.7

1.3

µs

Capacitive load for each bus line

400

400

pF

REPEATED START

START

STOP

START

SDA

SCL

4.7k

Ω

SDA

QST108

SCL

100

Ω

100

Ω

4.7k

Ω