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L6566ATR 数据表(PDF) 29 Page - STMicroelectronics |
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L6566ATR 数据表(HTML) 29 Page - STMicroelectronics |
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29 / 51 page ![]() L6566A Application information 29/51 Equation 7 The converter is then tested on the bench to find the output power level Poutlim where regulation is lost (because overcurrent is being tripped) both at Vin = Vinmin and Vin = Vinmax. If Poutlim @ Vinmax > Poutlim @ Vinmin the system is still undercompensated and k needs increasing; if Poutlim @ Vinmax < Poutlim @ Vinmin the system is overcompensated and k needs decreasing. This will go on until the difference between the two values is acceptably low. Once found the true kopt in this way, it is possible that Poutlim turns out slightly different from the target; to correct this, the sense resistor Rs needs adjusting and the above tuning process will be repeated with the new Rs value. Typically a satisfactory setting is achieved in no more than a couple of iterations. In applications where this function is not wanted, e.g. because the PFC stage regulates at a fixed voltage, the VFF pin can be simply grounded, directly or through a resistor (see “Chapter 5.11: OVP block on page 35”). The overcurrent setpoint will be then fixed at the maximum value of 1V. If a lower setpoint is desired to reduce the power dissipation on Rs, the pin can be also biased at a fixed voltage using a divider from VREF (pin 10). If the FF option is selected the Line Feedforward function can be still used to compensate for the total propagation delay Td of the current sense chain (internal propagation delay td(H-L) plus the turn-off delay of the external MOSFET), which in standard current mode PWM controllers is done by adding an offset on the current sense pin proportional to the input voltage. In that case the divider ratio k, which will be much smaller as compared to that used with the QR option selected, can be calculated with the following equation: Equation 8 max PKp min in opt I V 3 k 1 Rs − = Figure 17. Left: Overcurrent setpoint vs. VFF voltage; right: Line Feedforward function block Vcsx [V] 0 0.5 11.5 22.5 33.5 0 0.2 0.4 0.6 0.8 1 1.2 VVFF [V] VCOMP= Upper clamp 7 9 15 Rs PFC Output Bus DRIVER 4 R S Q R1B R2 COMP VFF CS GD L6566A 1.5 V Hiccup DISABLE VOLTAGE FEED FORWARD To PFC's OV sensing Optional for OVP settings OCP PWM Vcsx Clock/ZCD R1A Lp Rs Td 3 k opt = |
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