ST7263BH2T1 datasheet(96/145 Pages) STMICROELECTRONICS

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I²C bus interface (Cont’d)

I²C Clock Control Register (CCR)

Read / Write

Reset value: 0000 0000 (00h)

Bit 7 = FM/SM Fast/Standard I²C mode.

This bit is set and cleared by software. It is not

cleared when the interface is disabled (PE=0).

0: Standard I²C mode

1: Fast I²C mode

Bits 6:0 = CC[6:0] 7-bit clock divider.

These bits select the speed of the bus (FSCL) de-

pending on the I²C mode. They are not cleared

when the interface is disabled (PE=0).

Refer to the Electrical Characteristics section for

the table of value.

Note: The programmed FSCL assumes no load on

SCL and SDA lines.

I²C Data Register (DR)

Read / Write

Reset value: 0000 0000 (00h)

Bits 7:0 = D[7:0] 8-bit Data Register.

These bits contain the byte to be received or trans-

mitted on the bus.

– Transmitter mode: byte transmission start auto-

matically when the software writes in the DR reg-

ister.

– Receiver mode: the first data byte is received au-

tomatically in the DR register using the least sig-

nificant bit of the address.

Then, the following data bytes are received one

by one after reading the DR register.

I²C Own Address Register (OAR)

Read / Write

Reset value: 0000 0000 (00h)

Bits 7:1 = ADD[7:1] Interface address.

These bits define the I²C bus address of the inter-

face. They are not cleared when the interface is

disabled (PE=0).

Bit 0 = ADD0 Address direction bit.

This bit is don’t care, the interface acknowledges

either 0 or 1. It is not cleared when the interface is

disabled (PE=0).

Note: Address 01h is always ignored.

FM/SM

CC6

CC5

CC4

CC3

CC2

CC1

CC0

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

ADD0

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