ST7263BH2T1 datasheet(24/145 Pages) STMICROELECTRONICS

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7 Reset and clock management

7.1 Reset

The Reset procedure is used to provide an orderly

software start-up or to exit low power modes.

Three reset modes are provided: a low voltage

(LVD) reset, a watchdog reset and an external re-

set at the RESET pin.

A reset causes the reset vector to be fetched from

addresses FFFEh and FFFFh in order to be loaded

into the PC and with program execution starting

from this point.

An internal circuitry provides a 4096 CPU clock cy-

cle delay from the time that the oscillator becomes

active.

7.1.1 Low voltage detector (LVD)

Low voltage reset circuitry generates a reset when

VDD is:

■

below VIT+ when VDD is rising,

■

below VIT- when VDD is falling.

During low voltage reset, the RESET pin is held low,

thus permitting the MCU to reset other devices.

It is recommended to make sure that the VDD sup-

ply voltage rises monotonously when the device is

exiting from Reset, to ensure the application func-

tions properly.

7.1.2 Watchdog reset

When a watchdog reset occurs, the RESET pin is

pulled low permitting the MCU to reset other devic-

es in the same way as the low voltage reset (Fig-

ure 12).

7.1.3 External reset

The external reset is an active low input signal ap-

plied to the RESET pin of the MCU.

As shown in Figure 15, the RESET signal must

stay low for a minimum of one and a half CPU

clock cycles.

An internal Schmitt trigger at the RESET pin is pro-

vided to improve noise immunity.

Figure 12. Low voltage detector functional diagram

Figure 13. Low voltage reset signal output

Note: Hysteresis (VIT+-VIT-) = Vhys

Figure 14. Temporization timing diagram after an internal Reset

LOW VOLTAGE

VDD

FROM

WATCHDOG

RESET

INTERNAL

DETECTOR

RESET

VDD

VIT+

VIT-

VDD

Addresses

$FFFE

Temporization (4096 CPU clock cycles)

VIT+

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