AS8267 datasheet(39/136 Pages) AMSCO

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Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 39 of 136

MCU Debug Mode

When mdm flag of SREG/Status register is set, the DSP block enters the MCU debug mode. Here the MDR can

be written through the MCU interface. In this mode the DSP block is not allowed to write to the MDR.

Special functionality:

1) ack set to 0

→ np is set to 0 (i.e. must be set again by MCU)

2) when ack is not reset by the MCU the np value is doubled, i.e. a shift left is done.

Note: Also in debug mode an interrupt is generated after nsamp samples.

Power Supply Monitor (PSM)

The AS8267 / AS8268 ICs have an on-chip power supply monitor (PSM) that ensures a reset is generated

independently of the supply voltage (VDD) rise and fall times.

A built in hysteresis is provided to accommodate slow changes on the VDD, to ensure clean signal switching.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Threshold positive edge

Vth,pos

2.6

2.9

Threshold negative edge

Vth,neg

2.2

2.8

Hysteresis

Hyst

100

Table 1:

Power supply monitor: Power-on reset specifications

To ensure sufficient time is available to store the meter data in an EEPROM during power-down, it is necessary

to detect the falling supply voltage as fast as possible. Should only the VDD be monitored, an external

capacitor in the 3.3V power supply could sustain the VDD supply voltage even after the Vmains has begun to fall.

For this reason, the AS8267 / AS8268 ICs allow the monitoring of the Vmains to ensure early power-down

detection. The power-down detector function (PD_DET) is enabled in the SREG/Status register.

An alarm signal is generated, when the Vmains falls below a specified mains voltage threshold, which enables

the MCU to react with sufficient time. It is also possible to calculate energy during power-down detection,

taking a constant voltage value for calculation of the energy value.

The mains voltage threshold is calculated as follows:

)

ideal

(

RMS

512

)

alarm

(

mains

479

512

230

= 173.8 VAC

External System Reset (RES_N)

An external reset pin (RES_N) is provided for system reset. RES_N is active LOW (i.e. logic ‘0’ will initiate a

system reset). A system reset via the RES_N pin is OR-ed with the main system power-on reset generated by

the power supply monitor PSM.

RES_N is internally pulled high.

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