TLC3544, TLC3548

5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL

ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS

SLAS266C – OCTOBER 2000 – REVISED MAY 2003

13

POST OFFICE BOX 655303

CSTART trigger

PARAMETERS

MIN

TYP

MAX

UNIT

td(12)

Delay time, delay from CSTART rising edge to EOC falling

edge, at 10-pF load

0

15

21

ns

tw(4)

Pulse width CSTART low time: tW(L)(CSTART), at 25-pF load

t(sample – ref)+0.4

Note 7

µs

td(13)

Delay time, delay from CSTART rising edge to CSTART falling

edge, at 25-pF load

t(conv) +15

Notes 7 and 8

ns

td(14)

Delay time, delay from CSTART rising edge to INT falling edge,

at 10-pF load

t(conv) +15

Notes 7 and 8

t(conv)+21

ns

td(15)

Delay time, delay from CSTART falling edge to INT rising edge,

at 10-pF load

0

6

µs

NOTES:

7. The pulse width of CSTART must be not less than the required sampling time. The delay from CSTART rising edge to following

CSTART falling edge must not be less than the required conversion time. The delay from CSTART rising edge to the INT falling edge

is equal to the conversion time.

8. The maximum rate of SCLK is 25 MHz for normal long sampling and 10 MHz for normal short sampling.

t(conv)

OR

tw(4)

td(13)

td(12)

td(14)

td(15)

CSTART

EOC

INT

Extended Sampling

Figure 4. Critical Timing for Extended Sampling (CSTART Trigger)

detailed description

converter

The converters are a successive-approximation ADC utilizing a charge redistribution DAC. Figure 5 shows a

simplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the sampling

period. When the conversion process starts, the control logic directs the charge redistribution DAC to add and

subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition.

When balanced, the conversion is complete and the ADC output code is generated.