M41T94_07 datasheet(12/41 Pages) STMICROELECTRONICS

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Operation

M41T94

12/41

Operation

The M41T94 clock operates as a slave device on the SPI serial bus. Each memory device is

accessed by a simple serial interface that is SPI bus compatible. The bus signals are SCL,

SDI and SDO (see Table 1 on page 8 and Figure 5 on page 9). The device is selected when

the Chip Enable input (E) is held low. All instructions, addresses and data are shifted serially

in and out of the chip. The most significant bit is presented first, with the data input (SDI)

sampled on the first rising edge of the clock (SCL) after the Chip Enable (E) goes low. The

64 bytes contained in the device can then be accessed sequentially in the following order:

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1st byte: tenths/hundredths of a second register

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2nd byte: seconds register

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3rd byte: minutes register

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4th byte: century/hours register

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5th byte: day register

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6th byte: date register

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7th byte: month register

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8th byte: year register

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9th byte: control register

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10th byte: watchdog register

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11th - 16th bytes: Alarm registers

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17th - 19th bytes: reserved

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20th byte: square wave register

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21st - 64th bytes: user RAM

The M41T94 clock continually monitors VCC for an out-of tolerance condition. Should VCC

fall below VPFD, the device terminates an access in progress and resets the device address

counter. Inputs to the device will not be recognized at this time to prevent erroneous data

from being written to the device from a an out-of-tolerance system. When VCC falls below

VSO, the device automatically switches over to the battery and powers down into an ultra low

current mode of operation to conserve battery life. As system power returns and VCC rises

above VSO, the battery is disconnected, and the power supply is switched to external VCC.

Write protection continues until VCC reaches VPFD (min) plus tREC (min). For more

information on Battery Storage Life refer to Application Note AN1012.

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