M95128-RMB3GSLASHP datasheet(23/44 Pages) STMICROELECTRONICS

23 / 44 page

M95128, M95128-W, M95128-R

Instructions

23/44

Figure 11.

Page Write (WRITE) sequence

The most significant address bits (b15, b14) are Don’t Care.

5.6.1

ECC (error correction code) and Write cycling

The M95128 devices offer an ECC (error correction code) logic which compares each 4-byte

word with 6 EEPROM bits of ECC. As a result, if a single bit out of 4 bytes of data happens

to be erroneous during a Read operation, the ECC detects it and replaces it by the correct

value. The read reliability is therefore improved by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified

(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes

making up the word. It is therefore recommended to Write by packets of 4 bytes in order to

benefit from the larger amount of Write cycles.

The maximum number of Write cycles for the M95128 (range 6) device is qualified at 1

Million (1 000 000) Write cycles, using a cycling routine that writes to the device page by

page (that is, by multiples of 4-byte packets).

AI01796D

35 36 37 38 39 40 41 42

44 45 46 47

3456789 10

20 21 22 23 24 25 26 27

14 13

3210

28 29 30

Instruction

16-Bit Address

765432

Data Byte 1

765432

Data Byte 2

765432

Data Byte 3

65432

Data Byte N

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