8

S71GL-N Based MCPs

S71GL-N_00_02 June 19, 2007

Data

Sheet

(Adv an ce

Inf o r m a t io n)

5.

Ordering Information

The order number is formed by a valid combinations of the following:

Note

1. Type 0 is standard. Specify other options as required.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local

sales office to confirm availability of specific valid combinations and to check on newly released

combinations.

S71GL

064

N

A0

BF

W

0

Z

0

PACKING TYPE

0= Tray

2

= 7” Tape and Reel

3

= 13” Tape and Reel

MODEL NUMBER

See the Valid Combinations table.

PACKAGE MODIFIER

0

= 7 x 9 mm, 1.2 mm height, 56 balls (TLC056)

TEMPERATURE RANGE

W = Wireless (-25

PACKAGE TYPE

BF = Fine-pitch BGA Lead (Pb)-free package

pSRAM / SRAM DENSITY

B0 = 32 Mb pSRAM

A0 = 16 Mb pSRAM

40 = 4 Mb pSRAM

80 = 8 Mb pSRAM

PROCESS TECHNOLOGY

N

= 110 nm, MirrorBit Technology

FLASH DENSITY

064

= 64Mb

032

= 32Mb

PRODUCT FAMILY

S71GL Multi-chip Product (MCP)

3.0-volt Page Mode Flash Memory and RAM

Table 5.1 Valid Combinations

S71GL064N Valid Combinations

Speed Options (ns)/Boot

Sector Option

(p)SRAM Type/

Access Time

(ns)

Package

Marking

Base Ordering

Part Number

Package &

Temperature

Package Modifier/Model

Number

Packing Type

S71GL032N40

BFW

0K

0, 2, 3 (1)

90 / Bottom Boot Sector

pSRAM9 / 70

TLC056

0P

90 / Top Boot Sector

S71GL032N80

0K

90 / Bottom Boot Sector

pSRAM9 / 70

0P

90 / Top Boot Sector

S71GL032NA0

0U

90 / Bottom Boot Sector

pSRAM7 / 70

0Z

90 / Top Boot Sector

S71GL064NA0

0U

90 / Bottom Boot Sector

pSRAM7 / 70

S71GL064NA0

0Z

90 / Top Boot Sector

S71GL064NB0

0U

90 / Bottom Boot Sector

pSRAM8 / 70

S71GL064NB0

0Z

90 / Top Boot Sector