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74ACT74 数据表(PDF) 5 Page - Silicon Supplies |
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74ACT74 数据表(HTML) 5 Page - Silicon Supplies |
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5 / 6 page ![]() Page 5 of 6 www.siliconsupplies.com Advanced CMOS TTL Input – 74ACT74 Rev 1.0 21/11/19 Switching Waveforms Figure 1 – Data, Clock and Output Figure 2 – Set, Reset, Clock and Output Timing Requirements8 LIMITS PARAMETER SYMBOL VCC CONDITIONS 25°C 85°C FULL RANGE 4 UNITS Minimum Setup Time, D to CLK (Figure 3) tSU 5V ±10% CL = 50pF, Input tr = tf = 3ns 3 3.5 3.5 ns Minimum Hold Time, CLK to D (Figure 3) th 5V ±10% CL = 50pF, Input tr = tf = 3ns 1 1 1 ns Minimum Pulse Width, CLK, PRE, CLR (Figure 1) tw 5V ±10% CL = 50pF, Input tr = tf = 3ns 5 6 6 ns Maximum Recovery Time, PRE or CLR to CLK (Figure 2) trec 5V ±10% CL = 50pF, Input tr = tf = 3ns 0 0 0 ns |
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