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P912XDP512F0MPVR 数据表(PDF) 105 Page - Freescale Semiconductor, Inc |
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P912XDP512F0MPVR 数据表(HTML) 105 Page - Freescale Semiconductor, Inc |
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105 / 1350 page ![]() Chapter 2 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.17 Freescale Semiconductor 105 Figure 2-21. Wait Mode Entry/Exit Sequence Enter Wait Mode PLLWAI=1 ? Exit Wait w. CMRESET Exit Wait w. ext.RESET Exit Wait Mode Enter SCM Exit Wait Mode CPU Req’s Wait Mode. Clear PLLSEL, Disable PLL CME=1 ? INT ? CM Fail ? SCME=1 ? SCMIE=1 ? Continue w. Normal OP No No No No No Yes Yes Yes Yes Yes No Yes Wait Mode left due to external reset Generate SCM Interrupt (Wakeup from Wait) SCM=1 ? Enter SCM No Yes |
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