P912XDP512F0MFVR datasheet(333/1350 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

333

PAMOD

Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1).

0 Event counter mode

1 Gated time accumulation mode

PEDGE

Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled

(PAEN = 1). Refer to Table 7-19.

For PAMOD bit = 0 (event counter mode).

0 Falling edges on PT7 pin cause the count to be incremented

1 Rising edges on PT7 pin cause the count to be incremented

For PAMOD bit = 1 (gated time accumulation mode).

0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7

sets the PAIF ﬂag.

1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7

sets the PAIF ﬂag.

If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the

÷64 clock is generated by the

timer prescaler.

3:2

CLK[1:0]

Clock Select Bits — For the description of PACLK please refer to Figure 7-70.

If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input

clock to the timer counter. The change from one selected clock to the other happens immediately after these bits

are written. Refer to Table 7-20.

PAOVI

Pulse Accumulator A Overﬂow Interrupt Enable

0 Interrupt inhibited

1 Interrupt requested if PAOVF is set

PAI

Pulse Accumulator Input Interrupt Enable

0 Interrupt inhibited

1 Interrupt requested if PAIF is set

Table 7-19. Pin Action

PAMOD

PEDGE

Pin Action

Falling edge

Rising edge

Divide by 64 clock enabled with pin high level

Divide by 64 clock enabled with pin low level

Table 7-20. Clock Selection

CLK1

CLK0

Clock Source

Use timer prescaler clock as timer counter clock

Use PACLK as input to timer counter clock

Use PACLK/256 as timer counter clock frequency

Use PACLK/65536 as timer counter clock frequency

Table 7-18. PACTL Field Descriptions (continued)

Field

Description

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