P912XDP512F0MFVR datasheet(68/1350 Pages) FREESCALE

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Chapter 1 Device Overview MC9S12XD-Family

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

1.3

System Clock Description

The clock and reset generator module (CRG) provides the internal clock signals for the core and all

peripheral modules. Figure 1-12 shows the clock connections from the CRG to all modules.

See 79Chapterf or details on clock generation.

Figure 1-14. MC9S12XD Family Clock Connections

The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies

to be supported:

•

The on-chip phase locked loop (PLL)

•

the PLL self clocking

•

the oscillator

The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and

bus clock. As shown in Figure 1-12, this system clocks are used throughout the MCU to drive the core, the

memories, and the peripherals.

The program Flash memory and the EEPROM are supplied by the bus clock and the oscillator clock.The

oscillator clock is used as a time base to derive the program and erase times for the NVM’s. See the Flash

and EEPROM section for more details on the operation of the NVM’s.

SCI Modules

SPI Modules

IIC Modules

ATD Modules

CAN Modules

CRG

Bus Clock

EXTAL

XTAL

Core Clock

Oscillator Clock

RAM

S12X

XGATE

EEPROM

FLASH

PIT

ECT

PIM

P912XDP512F0MFVR 数据表(PDF) 68 Page - Freescale Semiconductor, Inc

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