P912XDP512F0MFVR datasheet(58/1350 Pages) FREESCALE

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Chapter 1 Device Overview MC9S12XD-Family

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

The XCLKS signal selects the oscillator conﬁguration during reset low phase while a clock quality check

is ongoing. This is the case for:

•

Power on reset or low-voltage reset

•

Clock monitor reset

•

Any reset while in self-clock mode or full stop mode

The selected oscillator conﬁguration is frozen with the rising edge of reset.

The pin can be conﬁgured to drive the internal system clock ECLKX2.

Figure 1-11. Loop Controlled Pierce Oscillator Connections (PE7 = 1)

Figure 1-12. Full Swing Pierce Oscillator Connections (PE7 = 0)

Figure 1-13. External Clock Connections (PE7 = 0)

1.2.3.17

PE6 / MODB / TAGHI — Port E I/O Pin 6

PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset.

The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a

MCU

EXTAL

XTAL

VSSPLL

Crystal or

Ceramic Resonator

MCU

EXTAL

XTAL

VSSPLL

Crystal or

Ceramic Resonator

MCU

EXTAL

XTAL

CMOS-Compatible

External Oscillator

Not Connected

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