P912XDP512F0MFVR datasheet(491/1350 Pages) FREESCALE

491 / 1350 page

Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

491

11.3.2.8

SCI Status Register 2 (SCISR2)

Read: Anytime

Write: Anytime

76543210

AMAP

TXPOL

RXPOL

BRK13

TXDIR

RAF

Reset

00000000

= Unimplemented or Reserved

Figure 11-11. SCI Status Register 2 (SCISR2)

Table 11-11. SCISR2 Field Descriptions

Field

Description

AMAP

Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset

condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and

status registers and hides the baud rate and SCI control Register 1.

0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible

1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible

TXPOL

Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by

a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA

format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal

polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for

inverted polarity.

0 Normal polarity

1 Inverted polarity

RXPOL

Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a

mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA

format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal

polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for

inverted polarity.

0 Normal polarity

1 Inverted polarity

BRK13

Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit

respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.

0 Break character is 10 or 11 bit long

1 Break character is 13 or 14 bit long

TXDIR

Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to

be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire

mode of operation.

0 TXD pin to be used as an input in single-wire mode

1 TXD pin to be used as an output in single-wire mode

RAF

Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start

bit search. RAF is cleared when the receiver detects an idle character.

0 No reception in progress

1 Reception in progress

P912XDP512F0MFVR 数据表(PDF) 491 Page - Freescale Semiconductor, Inc

P912XDP512F0MFVR 数据表(HTML) 491 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载