P912XDP512F0MFVR datasheet(547/1350 Pages) FREESCALE

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Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

547

13.3.0.4

PIT Multiplex Register (PITMUX)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

13.3.0.5

PIT Interrupt Enable Register (PITINTE)

Read: Anytime

Write: Anytime; writes to the reserved bits have no effect

76543210

0000

PMUX3

PMUX2

PMUX1

PMUX0

Reset

00000000

= Unimplemented or Reserved

Figure 13-6. PIT Multiplex Register (PITMUX)

Table 13-4. PITMUX Field Descriptions

Field

Description

3:0

PMUX[3:0]

PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to

micro time base 1 or 0. If PMUX is modiﬁed, the corresponding 16-bit timer is immediately switched to the other

micro time base.

0 The corresponding 16-bit timer counts with micro time base 0.

1 The corresponding 16-bit timer counts with micro time base 1.

76543210

0000

PINTE3

PINTE2

PINTE1

PINTE0

Reset

00000000

= Unimplemented or Reserved

Figure 13-7. PIT Interrupt Enable Register (PITINTE)

Table 13-5. PITINTE Field Descriptions

Field

Description

3:0

PINTE[3:0]

PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request

whenever the time-out ﬂag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)

enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF ﬂag has to be

cleared ﬁrst.

0 Interrupt of the corresponding PIT channel is disabled.

1 Interrupt of the corresponding PIT channel is enabled.

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