P912XDP512F0MFVR datasheet(559/1350 Pages) FREESCALE

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Chapter 14 Voltage Regulator (S12VREG3V3V5)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

559

14.3.2

This section describes all the VREG_3V3 registers and their individual bits.

14.3.2.1

HT Control Register (VREGHTCL)

The VREGHTCL is reserved for test purposes. This register should not be written.

14.3.2.2

Control Register (VREGCTRL)

The VREGCTRL register allows the conﬁguration of the VREG_3V3 low-voltage detect features.

76543210

00000000

Reset

00000000

= Unimplemented or Reserved

Figure 14-2. HT Control Register (VREGHTCL)

76543210

00000

LVDS

LVIE

LVIF

Reset

00000000

= Unimplemented or Reserved

Figure 14-3. Control Register (VREGCTRL)

Table 14-3. VREGCTRL Field Descriptions

Field

Description

LVDS

Low-Voltage Detect Status Bit — This read-only status bit reﬂects the input voltage. Writes have no effect.

0 Input voltage VDDA is above level VLVID or RPM or shutdown mode.

1 Input voltage VDDA is below level VLVIA and FPM.

LVIE

Low-Voltage Interrupt Enable Bit

0 Interrupt request is disabled.

1 Interrupt will be requested whenever LVIF is set.

LVIF

Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This ﬂag can only be cleared by

writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.

0 No change in LVDS bit.

1 LVDS bit has changed.

Note: On entering the reduced power mode the LVIF is not cleared by the VREG_3V3.

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