P912XDP512F0MFVR datasheet(571/1350 Pages) FREESCALE

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Chapter 15 Background Debug Module (S12XBDMV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

571

15.1.2.3

Low-Power Modes

The BDM can be used until all bus masters (e.g., CPU or XGATE) are in stop mode. When CPU is in a

low power mode (wait or stop mode) all BDM ﬁrmware commands as well as the hardware

BACKGROUND command can not be used respectively are ignored. In this case the CPU can not enter

BDM active mode, and only hardware read and write commands are available. Also the CPU can not enter

a low power mode during BDM active mode.

If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled

and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft

reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM

is now ready to receive a new command.

15.1.3

Block Diagram

A block diagram of the BDM is shown in Figure 15-1.

Figure 15-1. BDM Block Diagram

ENBDM

CLKSW

BDMACT

TRACE

SDV

16-Bit Shift Register

BKGD

Host

System

Serial

Interface

Data

Control

UNSEC

BDMSTS

Instruction Code

and

Execution

Standard BDM Firmware

LOOKUP TABLE

Secured BDM Firmware

LOOKUP TABLE

Bus Interface

and

Control Logic

Address

Data

Control

Clocks

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